(1) Field of the Invention
The present invention relates to the fabrication of integrated circuits, and more particularly to a method for making improved fuse structures on semiconductor integrated circuits, such as Dynamic Random Access Memory (DRAM) devices. This method uses a single masking step to etch the fuse openings in a passivation layer, while concurrently forming openings for bonding pads on the DRAM chip.
(2) Description of the Prior Art
Advances in semiconductor processing technologies, such as high-resolution photolithography and anisotropic plasma etching, are dramatically reducing the feature sizes of semiconductor devices and increasing the device packing density. Unfortunately, as the density of the semiconductor devices increases and the number of discrete devices increases on the chip, the final product yield for many integrated circuit devices (chip yield) decreases. For example, one circuit device that can experience this increase in yield loss with increased circuit elements is dynamic random access memory (DRAM) currently having 64 megabits of memory on a chip. After the year 2000 the number of memory cells is expected to increase further to about 1 to 4 gigabits, and high final product yield will be even more difficult to achieve without utilizing cell redundancy and repair yield methods.
One method of overcoming this lower yield on DRAM devices is to provide additional rows of memory cells and fusing each row of cells. Currently lasers are used to routinely open connections (fuses) in the multimegabit DRAMs to disable defective rows of memory cells and to modify the address decoder so that spare rows of memory cells are selected instead.
These fuse structures require additional processing steps that increases product cost. Typically three masking steps are required: one masking step is required to open the insulating layer over the fuse, a second mask is required to open the Si.sub.3 N.sub.4 layer over the bonding pad, and a third mask to etch the openings in the polyimide passivation layer. One method of reducing process cost is to combine the process steps for making the openings in a passivation layer over fuses and at the same time to make openings to other circuit elements on the DRAM chip, such as via openings, including bonding pad openings.
To better appreciate the problem associated with combining process steps for making these fuse windows and via openings, a schematic cross-sectional view of a fuse structure and a patterned first metal layer to which openings are made is depicted in FIG. 1. FIG. 1 shows a substrate 10. Typically the substrate 10 is partially completed to have diffused semiconductor devices, such as FETs having a patterned first polycide layer (not shown) for forming gate electrodes. An insulating layer 12 is then formed on the substrate to electrically insulate the devices. (These devices are not explicitly depicted in the Fig.) FIG. 1 shows a patterned second polycide layer 14 that is used to form electrical interconnections, such as bit lines for the DRAM devices. Typically the patterned polycide layer 14 includes portions for fuses, also labeled 14. Next a second insulating layer 16 is deposited and, after forming via holes (not shown), a first metal M1 layer 18 is deposited and patterned to form the next level of electrical interconnections. Typically layer 18 is aluminum/copper (Al/Cu) alloy having a titanium nitride (TiN) layer 20 on its surface that serves as an antireflective coating (ARC) when the M1 layer 18 is patterned using a photoresist mask and plasma etching. Next, a third insulating layer 22 is deposited to insulate the patterned M1 layer 18 having the ARC layer 20. Openings 2 are now etched in the insulating layers 22 and 16 over the fuses 14 to provide access for a laser abrasion, and concurrently openings 4 are etched in the insulating layer 22 to the M1 layer 18 to make contacts for the next level of metal M2. In this prior-art method, a single mask is used to etch openings 2 and 4 to reduce processing costs. Unfortunately, when the openings 2 over the fuses 14 are etched, the openings 4 for contacts are overetched causing damage to the underlying M1 layer 18 that can adversely affect the via contact resistance (R.sub.c) and metal electromigration lifetime. Further, the via profile can also be degraded due to excessive overetching. Another problem results when the second metal M2 layer is deposited and patterned. When the M2 layer 24 is anisotropically etched in the openings 2 over the fuses 14, it is difficult to completely remove the M2 metal residue 24' on the sidewalls of the fuses 14 because of the step height (high aspect ratio).
Various methods for making fuses on integrated circuits have been reported. For example, Okazaki, U.S. Pat. No. 5,753,539, teaches a method for making a fuse element in the same plane as a contact pad, therefore Okazaki can etch openings for both the fuse and contact pad in the insulating layer using a single mask. Since the opening to the fuse element is much smaller than the opening for the contact pad, the microloading effect during etching results in a slower etch rate over the fuse and therefore a thin portion of the insulating layer remains over the fuse to protect the fuse from moisture, while the contact pad is exposed in the contact pad opening. Fukahara et al. in U.S. Pat. No. 5,650,355 use various methods for forming fuses and bonding pads in which the fuses are protected by an oxide nitride layer while the openings to the bonding pads are etched. Chen, U.S. Pat. Nos. 5,712,206 and 5,538,924, describes methods for making moisture-impervious guard rings and moisture-barrier layers, respectively. The methods involve forming a moisture-resistant guard ring or a layer around the fuse window openings to prevent moisture contamination of the semiconductor circuit from the fuse area. Takayama et al., U.S. Pat. No. 4,536,949, describes a method for making more accurate fuse openings without increasing costs by etching an opening over the fuse each time an insulating layer is formed over the wiring for the integrated circuit. Boardman et al. in U.S. Pat. No. 5,290,734 describe a method for making reliable anti-fuse links in which a high-resistance material (1-2 gigaohms), such as an amorphous silicon, can be altered using a voltage across the amorphous silicon link, thereby reducing the resistance to about 200 ohms. This method replaces titanium and titanium tungsten fuses and requires less space on the integrated circuit.
There is still a strong need in the semiconductor industry to further improve the method for making reliable and repeatable fuse structures which are manufacturing cost effective.